Dr David Boland

MEng, PhD
Lecturer in Electrical Engineering
School of Electrical and Information Engineering

J03 - Electrical Engineering Building
The University of Sydney

Telephone +61 2 9351 7230

Website Computer, software and electronic engineering

School of Electrical and Information Engineering

Biographical details

Dr. David Boland completed his MEng. and PhD. at Imperial College London in 2007 and 2012 respectively. He worked at Monash University as a lecturer from 2013 to 2016, before moving to the University of Sydney in 2017.

Research interests

One of the advantages of today’s personal computers is that they’re able to operate a wide range of different software programs. The flipside of this flexibility, however, is that any given software program is unlikely to make use of all the available hardware. Dr David Boland’s research focuses on this issue, with the aim of achieving faster and more energy-efficient computing.
“I study the computer algorithms used to solve problems across many domains, including scientific computing, machine learning and optical communications.

“I then consider how to design fully customised hardware solutions to these problems. In doing this I focus on how to perform as little computation as necessary, while still obtaining results as accurate as those produced by the original algorithm used in the software. This helps to maximise energy efficiency. I also look at how to do as much parallel computation as possible, in order to maximise performance.

“The technology to support this exists: we can already create application-specific integrated circuits, and we can use field-programmable gate arrays on which custom hardware designs can be programmed after manufacturing. However, designing customised hardware architectures is challenging, so is currently restricted to experts. I’m interested in making this performance more widely accessible.

“My research to date has largely focused on accelerating common computational kernels and basic arithmetic structures. I’m currently working on creating custom hardware accelerators for machine learning within the context of analysing wireless communication systems.

“The ability to perform fast analysis and prediction using this information could be critical for effective military operations, for example. High-performance and energy-efficient computation is also critical for the development and widespread use of novel technologies such as artificial intelligence, which could transform society. The challenge is to develop design techniques that are of benefit both now and in the future.

“I’ve been working in this field since 2007, and I joined the University of Sydney in 2017. The University has provided me with more opportunities to engage with industry and to work alongside like-minded colleagues to maximise the impact of my research.”

Selected grants

2017

  • MyIP: CERA 169 Fast Automated anomaly detection in communication networks. DSTG funded research agreement.; Boland D, Leong P; Defence Science and Technology Group/Client Commissioned Research.

Selected publications

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Book Chapters

  • Constantinides, G., Bayliss, S., Boland, D. (2015). Whither reconfigurable computing? In Wayne Luk, George A Constantindes (Eds.), Transforming Reconfigurable Systems, (pp. 19-38). London: Imperial College Press. [More Information]

Journals

  • Moses M, J., Sinha, A., Boland, D. (2017). Geometric Pattern Formation on a Plane Under a General Graph Topology. IFAC-PapersOnLine, 50(1), 2391-2396. [More Information]
  • Wang, Q., Song, B., Corcoran, B., Boland, D., Zhu, C., Zhuang, L., Lowery, A. (2017). Hardware-efficient signal generation of layered/enhanced ACO-OFDM for short-haul fiber-optic links. Optics Express, 25(12), 13359-13371. [More Information]
  • Shi, K., Boland, D., Constantinides, G. (2015). Imprecise datapath design: An overclocking approach. ACM Transactions on Reconfigurable Technology and Systems, 8(2), 1-23. [More Information]
  • Boland, D., Constantinides, G. (2013). A scalable precision analysis framework. IEEE Transactions on Multimedia, 15(2), 242-256. [More Information]
  • Boland, D., Constantinides, G. (2011). Bounding Variable Values and Round-Off Effects Using Handelman Representations. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 30(11), 1691-1704. [More Information]
  • Boland, D., Constantinides, G. (2011). Optimizing Memory Bandwidth Use and Performance for Matrix-Vector Multiplication in Iterative Methods. ACM Transactions on Reconfigurable Technology and Systems, 4(3), 1-14. [More Information]
  • Stamm, R., Boland, D., Hammami, R., Capes, H., Catoire, F., Koubiti, M., Mekkaoui, A., Marandet, Y., Rosato, J., et al (2011). Stochastic processes applied to line shapes. Baltic Astronomy, 20(4), 540-547.

Conferences

  • Fox, S., Boland, D., Leong, P. (2018). FPGA Fastfood - a high speed systolic implementation of a large scale online kernel method. 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2018), New York: ACM Digital Library. [More Information]
  • Moss, D., Boland, D., Pourbeik, P., Leong, P. (2018). Real-time FPGA-based Anomaly Detection for Radio Frequency Signals. 2018 IEEE International Symposium on Circuits and Systems Nano-Bio Circuit Fabrics and Systems (ISCAS), Piscataway: Institute of Electrical and Electronics Engineers (IEEE). [More Information]
  • Schmidt, S., Boland, D. (2017). Dynamic bitwidth assignment for efficient dot products. 27th International Conference on Field Programmable Logic and Applications, FPL 2017, Piscataway, NJ: Institute of Electrical and Electronics Engineers Inc. [More Information]
  • Weberruss, J., Kleeman, L., Boland, D., Drummond, T. (2017). FPGA acceleration of multilevel ORB feature extraction for computer vision. 27th International Conference on Field Programmable Logic and Applications, FPL 2017, Piscataway, NJ: Institute of Electrical and Electronics Engineers Inc. [More Information]
  • Shi, K., Boland, D., Constantinides, G. (2016). Efficient FPGA implementation of digit parallel online arithmetic operators. 2014 International Conference on Field- Programmable Technology (ICFPT), Danvers: Institute of Electrical and Electronics Engineers (IEEE). [More Information]
  • Boland, D. (2016). Reducing memory requirements for high-performance and numerically stable Gaussian elimination. FPGA'16 The 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, New York: Association for Computing Machinery (ACM). [More Information]
  • Shi, K., Boland, D., Stott, E., Bayliss, S., Constantinides, G. (2014). Datapath synthesis for overclocking: Online arithmetic for latency-accuracy trade-offs. 51st Annual Design Automation Conference (DAC 2014), New York: Association for Computing Machinery (ACM). [More Information]
  • Shi, K., Boland, D., Constantinides, G. (2013). Accuracy-performance tradeoffs on an FPGA through overclocking. 21st Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2013), Piscataway: Institute of Electrical and Electronics Engineers (IEEE). [More Information]
  • Shi, K., Boland, D., Constantinides, G. (2013). Overclocking datapath for latency-error tradeoff. 2013 IEEE International Symposium on Circuits and Systems (ISCAS 2013), Beijing: Institute of Electrical and Electronics Engineers (IEEE). [More Information]
  • Boland, D., Constantinides, G. (2013). Revisiting the reduction circuit: a case study for simultaneous architecture and precision optimisation. 2013 12th International Conference on Field Programmable Technology (FPT 2013), Piscataway: Institute of Electrical and Electronics Engineers (IEEE). [More Information]
  • Boland, D., Constantinides, G. (2013). Word-length optimization beyond straight line code. 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA 2013), New York: Association for Computing Machinery (ACM). [More Information]
  • Boland, D., Constantinides, G. (2012). A Scalable Approach for Automated Precision Analysis. 2012 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA 2012), New York: ACM Digital Library. [More Information]
  • Hammami, R., Boland, D., Capes, H., Christova, M., Marandet, Y., Rosato, J., Stamm, R. (2012). A Stark broadening simulation using a renewal process for the electric microfield. XXI International Conference on Spectral Line Shapes (ICSLS 2012), Bristol: IOP Publishing. [More Information]
  • Tan, X., Boland, D., Constantinides, G. (2012). FPGA paranoia: Testing numerical properties of FPGA floating point IP-cores. 8th International Symposium on Applied Reconfigurable Computing (ARC 2012), Berlin: Springer Verlag. [More Information]
  • Le Lann, C., Boland, D., Constantinides, G. (2011). The Krawczyk Algorithm:Rigorous Bounds for Linear Equation Solution on an FPGA. 7th International Symposium on Applied Reconfigurable Computing (ARC 2011), Berlin: Springer Verlag. [More Information]

Reference Works

  • Boland, D., Cheng, C., Kahng, A., Leong, P. (2017). Reconfigurable Computing. In John G Webster (Eds.), Wiley Encyclopedia of Electrical and Electronics Engineering. (pp. 1-17). 10.1002/047134608X.W7603.pub3: Wiley.

2018

  • Fox, S., Boland, D., Leong, P. (2018). FPGA Fastfood - a high speed systolic implementation of a large scale online kernel method. 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2018), New York: ACM Digital Library. [More Information]
  • Moss, D., Boland, D., Pourbeik, P., Leong, P. (2018). Real-time FPGA-based Anomaly Detection for Radio Frequency Signals. 2018 IEEE International Symposium on Circuits and Systems Nano-Bio Circuit Fabrics and Systems (ISCAS), Piscataway: Institute of Electrical and Electronics Engineers (IEEE). [More Information]

2017

  • Schmidt, S., Boland, D. (2017). Dynamic bitwidth assignment for efficient dot products. 27th International Conference on Field Programmable Logic and Applications, FPL 2017, Piscataway, NJ: Institute of Electrical and Electronics Engineers Inc. [More Information]
  • Weberruss, J., Kleeman, L., Boland, D., Drummond, T. (2017). FPGA acceleration of multilevel ORB feature extraction for computer vision. 27th International Conference on Field Programmable Logic and Applications, FPL 2017, Piscataway, NJ: Institute of Electrical and Electronics Engineers Inc. [More Information]
  • Moses M, J., Sinha, A., Boland, D. (2017). Geometric Pattern Formation on a Plane Under a General Graph Topology. IFAC-PapersOnLine, 50(1), 2391-2396. [More Information]
  • Wang, Q., Song, B., Corcoran, B., Boland, D., Zhu, C., Zhuang, L., Lowery, A. (2017). Hardware-efficient signal generation of layered/enhanced ACO-OFDM for short-haul fiber-optic links. Optics Express, 25(12), 13359-13371. [More Information]
  • Boland, D., Cheng, C., Kahng, A., Leong, P. (2017). Reconfigurable Computing. In John G Webster (Eds.), Wiley Encyclopedia of Electrical and Electronics Engineering. (pp. 1-17). 10.1002/047134608X.W7603.pub3: Wiley.

2016

  • Shi, K., Boland, D., Constantinides, G. (2016). Efficient FPGA implementation of digit parallel online arithmetic operators. 2014 International Conference on Field- Programmable Technology (ICFPT), Danvers: Institute of Electrical and Electronics Engineers (IEEE). [More Information]
  • Boland, D. (2016). Reducing memory requirements for high-performance and numerically stable Gaussian elimination. FPGA'16 The 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, New York: Association for Computing Machinery (ACM). [More Information]

2015

  • Shi, K., Boland, D., Constantinides, G. (2015). Imprecise datapath design: An overclocking approach. ACM Transactions on Reconfigurable Technology and Systems, 8(2), 1-23. [More Information]
  • Constantinides, G., Bayliss, S., Boland, D. (2015). Whither reconfigurable computing? In Wayne Luk, George A Constantindes (Eds.), Transforming Reconfigurable Systems, (pp. 19-38). London: Imperial College Press. [More Information]

2014

  • Shi, K., Boland, D., Stott, E., Bayliss, S., Constantinides, G. (2014). Datapath synthesis for overclocking: Online arithmetic for latency-accuracy trade-offs. 51st Annual Design Automation Conference (DAC 2014), New York: Association for Computing Machinery (ACM). [More Information]

2013

  • Boland, D., Constantinides, G. (2013). A scalable precision analysis framework. IEEE Transactions on Multimedia, 15(2), 242-256. [More Information]
  • Shi, K., Boland, D., Constantinides, G. (2013). Accuracy-performance tradeoffs on an FPGA through overclocking. 21st Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2013), Piscataway: Institute of Electrical and Electronics Engineers (IEEE). [More Information]
  • Shi, K., Boland, D., Constantinides, G. (2013). Overclocking datapath for latency-error tradeoff. 2013 IEEE International Symposium on Circuits and Systems (ISCAS 2013), Beijing: Institute of Electrical and Electronics Engineers (IEEE). [More Information]
  • Boland, D., Constantinides, G. (2013). Revisiting the reduction circuit: a case study for simultaneous architecture and precision optimisation. 2013 12th International Conference on Field Programmable Technology (FPT 2013), Piscataway: Institute of Electrical and Electronics Engineers (IEEE). [More Information]
  • Boland, D., Constantinides, G. (2013). Word-length optimization beyond straight line code. 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA 2013), New York: Association for Computing Machinery (ACM). [More Information]

2012

  • Boland, D., Constantinides, G. (2012). A Scalable Approach for Automated Precision Analysis. 2012 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA 2012), New York: ACM Digital Library. [More Information]
  • Hammami, R., Boland, D., Capes, H., Christova, M., Marandet, Y., Rosato, J., Stamm, R. (2012). A Stark broadening simulation using a renewal process for the electric microfield. XXI International Conference on Spectral Line Shapes (ICSLS 2012), Bristol: IOP Publishing. [More Information]
  • Tan, X., Boland, D., Constantinides, G. (2012). FPGA paranoia: Testing numerical properties of FPGA floating point IP-cores. 8th International Symposium on Applied Reconfigurable Computing (ARC 2012), Berlin: Springer Verlag. [More Information]

2011

  • Boland, D., Constantinides, G. (2011). Bounding Variable Values and Round-Off Effects Using Handelman Representations. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 30(11), 1691-1704. [More Information]
  • Boland, D., Constantinides, G. (2011). Optimizing Memory Bandwidth Use and Performance for Matrix-Vector Multiplication in Iterative Methods. ACM Transactions on Reconfigurable Technology and Systems, 4(3), 1-14. [More Information]
  • Stamm, R., Boland, D., Hammami, R., Capes, H., Catoire, F., Koubiti, M., Mekkaoui, A., Marandet, Y., Rosato, J., et al (2011). Stochastic processes applied to line shapes. Baltic Astronomy, 20(4), 540-547.
  • Le Lann, C., Boland, D., Constantinides, G. (2011). The Krawczyk Algorithm:Rigorous Bounds for Linear Equation Solution on an FPGA. 7th International Symposium on Applied Reconfigurable Computing (ARC 2011), Berlin: Springer Verlag. [More Information]

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